Testing requirements for emerging single-chip cryogenic mixed-signal quantum processors in production FDSOI CMOS technology
Testing requirements for emerging single-chip cryogenic mixed-signal quantum processors in production FDSOI CMOS technology
Thursday, November 14, 2019: 2:05 PM
F 150/151 (Oregon Convention Center)
Summary:
This presentation will discuss testing requirements and challenges for two mixed-signal quantum processor architectures based on charge and spin qubits, respectively, monolithically integrated with readout and microwave/mm-wave control electronics in commercial 22nm FDSOI CMOS technology, and intended for operation at 4-12 Kelvin. Both qubit schemes rely on minimum size MOSFETs and multi-gate cascodes operated in the subthreshold region for the quantum core. Qubit, circuit, and technology characterization on-die at cryogenic temperatures and up to 67 GHz will be discussed.
This presentation will discuss testing requirements and challenges for two mixed-signal quantum processor architectures based on charge and spin qubits, respectively, monolithically integrated with readout and microwave/mm-wave control electronics in commercial 22nm FDSOI CMOS technology, and intended for operation at 4-12 Kelvin. Both qubit schemes rely on minimum size MOSFETs and multi-gate cascodes operated in the subthreshold region for the quantum core. Qubit, circuit, and technology characterization on-die at cryogenic temperatures and up to 67 GHz will be discussed.