EOS Failure in Low-Voltage Core Circuits during Latch-up Test at I/O Pins
EOS Failure in Low-Voltage Core Circuits during Latch-up Test at I/O Pins
Thursday, October 31, 2024
Indigo Ballroom (Hilton San Diego Bayfront)
Summary:
This work explored the complexities of EOS failures in low-voltage core circuits induced by latch-up test at I/O pins, focusing on the impact of abnormal LDO output voltages. Through detailed failure analysis and experimental validation with test chips, the root cause of EOS failures has been identified, and effective mitigation strategies were proposed. The modified design, by incorporating DNW-isolated NMOS structures, has demonstrated significant improvements in suppressing abnormal LDO output voltages, thereby mitigating EOS issues. Additionally, alternative compensation network configurations, such as employing MOM capacitors, were also shown to be effective in addressing abnormal LDO outputs.
This work explored the complexities of EOS failures in low-voltage core circuits induced by latch-up test at I/O pins, focusing on the impact of abnormal LDO output voltages. Through detailed failure analysis and experimental validation with test chips, the root cause of EOS failures has been identified, and effective mitigation strategies were proposed. The modified design, by incorporating DNW-isolated NMOS structures, has demonstrated significant improvements in suppressing abnormal LDO output voltages, thereby mitigating EOS issues. Additionally, alternative compensation network configurations, such as employing MOM capacitors, were also shown to be effective in addressing abnormal LDO outputs.