Targeted TEM SRAM-like Analysis Without Delayering
Targeted TEM SRAM-like Analysis Without Delayering
Wednesday, October 30, 2024: 10:20 AM
204 (Hilton San Diego Bayfront)
Summary:
In the ever increasing complexity of today’s state-of-the-art semiconductor structures it is desirable to seek any advantage in the fault isolation and analysis paradigm to improve time to data. This paper discusses one such improvement where it is shown to be possible to target silicon (Si) devices, their metal contacts, or any other location in the wafer stack in an SRAM test structure from metal level 7 (M7) for transmission electron microscopy (TEM) sample fabrication using a modified sample geometry, focused ion beam (FIB) software targeting tools, and planning for failure analysis at the mask design stage. Demonstration of this process is shown within this paper using electron beam inspection (EBI) data obtained at the contact level for a wafer that went through additional processing steps to M7. This process has a significant advantage when working with bit fail maps in SRAM arrays where a subset of failure modes can be pinpointed to specific locations in the layout based upon electrical data alone. The more standard practice for SRAM failures involves extensive delayering of metal levels down to at least metal level 1 (M1) with further isolation and characterization of the failure mode before proceeding to final physical analysis by TEM [1-3].
In the ever increasing complexity of today’s state-of-the-art semiconductor structures it is desirable to seek any advantage in the fault isolation and analysis paradigm to improve time to data. This paper discusses one such improvement where it is shown to be possible to target silicon (Si) devices, their metal contacts, or any other location in the wafer stack in an SRAM test structure from metal level 7 (M7) for transmission electron microscopy (TEM) sample fabrication using a modified sample geometry, focused ion beam (FIB) software targeting tools, and planning for failure analysis at the mask design stage. Demonstration of this process is shown within this paper using electron beam inspection (EBI) data obtained at the contact level for a wafer that went through additional processing steps to M7. This process has a significant advantage when working with bit fail maps in SRAM arrays where a subset of failure modes can be pinpointed to specific locations in the layout based upon electrical data alone. The more standard practice for SRAM failures involves extensive delayering of metal levels down to at least metal level 1 (M1) with further isolation and characterization of the failure mode before proceeding to final physical analysis by TEM [1-3].