Analysis of 3row failure caused by vulnerable data retention failure adjacent to disconnected BCAT.
Analysis of 3row failure caused by vulnerable data retention failure adjacent to disconnected BCAT.
Thursday, October 31, 2024
Indigo Ballroom (Hilton San Diego Bayfront)
Summary:
As the size of Dynamic Random Access Memory (DRAM) chips continues to shrink, the density and complexity increase, leading to closer proximity between word lines. This proximity raises concerns regarding adjacent word line interference during device operation. Such interference poses a significant risk of data retention failure, highlighting emerging defects in DRAM technology. This study presents a novel case of dynamic data retention failure that occurs in adjacent locations of word lines with disconnected Buried Channel Array Transistor (BCAT). Besides this interaction failure results in 3row failure which will use 3row Redundancy. This was examined under varying conditions of voltage, temperature, and test orientation. Through experimental analysis and fault characterization, it was confirmed that the increase in data retention failure was due to pass gate effect adjacent to disconnected BCAT failure Word line. These results underscore the importance of comprehensive testing and analysis in uncovering and mitigating emerging defects in advanced DRAM technology, contributing to the ongoing efforts to improve performance and enhance memory reliability in computing systems.
As the size of Dynamic Random Access Memory (DRAM) chips continues to shrink, the density and complexity increase, leading to closer proximity between word lines. This proximity raises concerns regarding adjacent word line interference during device operation. Such interference poses a significant risk of data retention failure, highlighting emerging defects in DRAM technology. This study presents a novel case of dynamic data retention failure that occurs in adjacent locations of word lines with disconnected Buried Channel Array Transistor (BCAT). Besides this interaction failure results in 3row failure which will use 3row Redundancy. This was examined under varying conditions of voltage, temperature, and test orientation. Through experimental analysis and fault characterization, it was confirmed that the increase in data retention failure was due to pass gate effect adjacent to disconnected BCAT failure Word line. These results underscore the importance of comprehensive testing and analysis in uncovering and mitigating emerging defects in advanced DRAM technology, contributing to the ongoing efforts to improve performance and enhance memory reliability in computing systems.