IC Backside De-processing Physical Failure Analysis with Laser Ablation Technique
IC Backside De-processing Physical Failure Analysis with Laser Ablation Technique
Thursday, October 31, 2024
Indigo Ballroom (Hilton San Diego Bayfront)
Summary:
This paper introduces an innovative backside de-processing method for integrated circuits (ICs) utilizing laser ablation, enhancing failure analysis (FA) capabilities for automotive non-volatile memories (NVMs) and advancing semiconductor FA methodologies. The proposed technique involves thinning the backside silicon (Si) substrate via laser ablation and subsequent chemical etching to reveal front-end-of-line (FEOL) defects. Experimental results demonstrate enhanced sample handling, reduced preparation time, and superior performance compared to conventional methods.
This paper introduces an innovative backside de-processing method for integrated circuits (ICs) utilizing laser ablation, enhancing failure analysis (FA) capabilities for automotive non-volatile memories (NVMs) and advancing semiconductor FA methodologies. The proposed technique involves thinning the backside silicon (Si) substrate via laser ablation and subsequent chemical etching to reveal front-end-of-line (FEOL) defects. Experimental results demonstrate enhanced sample handling, reduced preparation time, and superior performance compared to conventional methods.