Invited Talk: Majid Vaghayenegar, ThermoFisher Scientific, presents, "Meeting Current and Future Challenges on Advanced Circuit Edit Technologies".
Authors: Majid Vaghayenegar1, Alex Buxbaum1, David Donnet2, and Roisin Kelly2
1ThermoFisher Scientific, 3400 W Warren Ave, Fremont, CA, 94538
2Thermo Fisher Scientific, Achtseweg Noord 5, 5651 GG, Eindhoven, The Netherlands
Abstract
Circuit edit (CE) plays a fundamental role in semiconductor design debug leading to product cycle time improvements [1]. Advanced technology nodes pose new challenges to circuit edit, example shrinking STI-gate distances and introduction of new architectures such as backside power delivery. In this talk, we will review FIB CE hardware innovations that were made to enable advanced circuit edit. These innovations include fundamental resolution improvements needed to image ever shrinking features. In addition, correction for system drift for higher placement accuracy is extremely important. New application workflows at fA beam currents and low kV ensure minimal device performance degradation to meet the CE demands of 3 and 5nm products [2, 3].
References
[1] B. Herschbein, et al., “FinFET Transistor Output Drive Performance Modification by Focused Ion Beam (FIB) Chip Circuit Editing”, Proceedings of the ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis. p. 122-128. DOI: 10.31399/asm.cp.istfa2020p0122
[2] Haimson. et al., “Electrical characterization of circuit edit workflow using high and low energy FIB”, Proceedings of the ISTFA 2022: Papers Accepted for the Planned 48th International Symposium for Testing and Failure Analysis. p. 176-178. https://doi.org/10.31399/asm.cp.istfa2022p0176
[3] Yan. et al., “Low-kV FIB applications and workflows for advanced circuit edit”, Proceedings of the ISTFA 2023: Papers Accepted for the Planned 49th International Symposium for Testing and Failure Analysis. p. 300-304. https://doi.org/10.31399/asm.cp.istfa2023p0300
Biography
Majid Vaghayenegar received his Ph.D. in Materials Science and Engineering from Arizona State University in 2017. He is an experienced microscopist and materials engineer with a demonstrated history of working in the Magnetic Storage and Semiconductor industries. He is skilled in Electron Microscopy techniques, Materials Characterization, and Circuit Edit applications.
Jayant D'Souza, SIEMENS USA and Mr. Saidapet Ramesh, NXP Semiconductors