A Practical Tutorial on Electrical Fault Isolation of Digital SoCs
A Practical Tutorial on Electrical Fault Isolation of Digital SoCs
Monday, November 17, 2025: 3:00 PM
2 (Pasadena Convention Center)
Summary:
Failure Analysis (FA) plays a critical role in the silicon bring up, yield ramp up and product health, identifying key design weaknesses, process technology marginalities and test-related problems. With the increasing complexity of chip integration and design, process technology scaling and the advent of complex package configurations, failure analysis becomes even more important as new failure mechanisms evolve while optical fault isolation continues to face a lot of challenges (optical resolution, test pattern complexity). This tutorial aims to present a practical overview of Automated Test Equipment (ATE)-Based Electrical Fault Isolation (EFI) techniques. EFI is one of the major steps during failure analysis. Despite the presence of logic or memory diagnostics, EFI is sometimes still required to further reduce the area of interest for PFA or increase the confidence level on the diagnostic callouts. Fault isolation increases the chances of success for PFA and improves the efficiency of the FA process. The tutorial will be focusing on two key Optical Fault Isolation (OFI) techniques using the ATE: Photon Emission Microscopy (PEM) and Laser Voltage Imaging and Probing (LVX). The tutorial will be broken down into several sections. A quick introduction showing the importance of EFI to the overall success of the FA process will be presented. The tutorial will cover the components of ATE failure verification, which includes identifying different failure modes and fault models associated with them. In addition, some basic concepts on Design for Test and logic/memory diagnostics will be presented. The basics of scan chain integrity, stuck-at-fault (SAF) and transition-delay fault testing will be explained, together with the challenges and requirements for Electrical Fault Isolation (EFI). Since the aim of the tutorial is to give a practical overview of how these techniques are performed, the test stimulus and hardware requirements of such techniques shall also be presented. As the both process and package technology becomes complex (3DIC, Gate-All-Around, Backside Power Delivery Network, etc.), the current challenges of electrical fault isolation will also be discussed. Lastly, a small section will cover some advanced and emerging EFI technologies such as the Embedded Deterministic Test (EDT) and Streaming Scan Network (SSN). The tutorial will aim to introduce a new feature in SSN that is specifically made to enable Laser Voltage Imaging and is called the “LVX mode”. During the tutorial, the basic architecture, usage and advantages of the LVX mode will be presented. The goal of this tutorial is to provide an overview and not to go into deep dive of the physics behind the techniques, with the intention to provide the audience with an idea of how ATE-based EFI is performed on digital SoCs.
Failure Analysis (FA) plays a critical role in the silicon bring up, yield ramp up and product health, identifying key design weaknesses, process technology marginalities and test-related problems. With the increasing complexity of chip integration and design, process technology scaling and the advent of complex package configurations, failure analysis becomes even more important as new failure mechanisms evolve while optical fault isolation continues to face a lot of challenges (optical resolution, test pattern complexity). This tutorial aims to present a practical overview of Automated Test Equipment (ATE)-Based Electrical Fault Isolation (EFI) techniques. EFI is one of the major steps during failure analysis. Despite the presence of logic or memory diagnostics, EFI is sometimes still required to further reduce the area of interest for PFA or increase the confidence level on the diagnostic callouts. Fault isolation increases the chances of success for PFA and improves the efficiency of the FA process. The tutorial will be focusing on two key Optical Fault Isolation (OFI) techniques using the ATE: Photon Emission Microscopy (PEM) and Laser Voltage Imaging and Probing (LVX). The tutorial will be broken down into several sections. A quick introduction showing the importance of EFI to the overall success of the FA process will be presented. The tutorial will cover the components of ATE failure verification, which includes identifying different failure modes and fault models associated with them. In addition, some basic concepts on Design for Test and logic/memory diagnostics will be presented. The basics of scan chain integrity, stuck-at-fault (SAF) and transition-delay fault testing will be explained, together with the challenges and requirements for Electrical Fault Isolation (EFI). Since the aim of the tutorial is to give a practical overview of how these techniques are performed, the test stimulus and hardware requirements of such techniques shall also be presented. As the both process and package technology becomes complex (3DIC, Gate-All-Around, Backside Power Delivery Network, etc.), the current challenges of electrical fault isolation will also be discussed. Lastly, a small section will cover some advanced and emerging EFI technologies such as the Embedded Deterministic Test (EDT) and Streaming Scan Network (SSN). The tutorial will aim to introduce a new feature in SSN that is specifically made to enable Laser Voltage Imaging and is called the “LVX mode”. During the tutorial, the basic architecture, usage and advantages of the LVX mode will be presented. The goal of this tutorial is to provide an overview and not to go into deep dive of the physics behind the techniques, with the intention to provide the audience with an idea of how ATE-based EFI is performed on digital SoCs.