Die Level Fault Isolation - Failure Defect Modeling and Offset Voltage Calculator to determine the Effect of PMOS Threshold Voltage Shift and Resistance Mismatch of Segmented Digital-to-Analog Converter
Die Level Fault Isolation - Failure Defect Modeling and Offset Voltage Calculator to determine the Effect of PMOS Threshold Voltage Shift and Resistance Mismatch of Segmented Digital-to-Analog Converter
Wednesday, November 19, 2025
Summary:
Test Engineering group encountered a burn-in failure of a Precision Instrumentation Integrated Circuit (IC) from Safelaunch Activity with 100mV offset on Multiplexer Test parameter. Failure Analysis group confirmed the 100mV DAC Offset Voltage (Vos) failure. Fault Localization activity was challenging because it required multiple FA techniques to isolate the failing transistor in the Segmented Digital-to-Analog Converter (DAC) circuitry such as Light Emission Microscopy (LEM), Optical Beam Induced Resistance Change (OBIRCH), mechanical microprobing, bench testing pre- and post-baking, parallel lapping, then nanoprobing analysis. Further discussion/collaboration with designer resulted in confirming the fault through nanoprobing of the two PMOS transistors of the Differential Amplifier which revealed the Vth Shift of the PMOS transistors. This paper aims to speed-up the circuit analysis of DAC failures, using Nodal Analysis and Thevenin’s Theorem to calculate the DAC output, and model the failure on the cause of the DAC Offset Voltage failure. A Segmented DAC Offset Voltage Calculator was created to easily determine the fault coming from a PMOS Threshold Voltage (Vth) shift or a resistance mismatch of the resistor network. Circuit Simulation validated the calculated values from the DAC Offset Voltage Calculator. Nine (9) case studies were done to validate the calculated data with respect to the simulation data.
Test Engineering group encountered a burn-in failure of a Precision Instrumentation Integrated Circuit (IC) from Safelaunch Activity with 100mV offset on Multiplexer Test parameter. Failure Analysis group confirmed the 100mV DAC Offset Voltage (Vos) failure. Fault Localization activity was challenging because it required multiple FA techniques to isolate the failing transistor in the Segmented Digital-to-Analog Converter (DAC) circuitry such as Light Emission Microscopy (LEM), Optical Beam Induced Resistance Change (OBIRCH), mechanical microprobing, bench testing pre- and post-baking, parallel lapping, then nanoprobing analysis. Further discussion/collaboration with designer resulted in confirming the fault through nanoprobing of the two PMOS transistors of the Differential Amplifier which revealed the Vth Shift of the PMOS transistors. This paper aims to speed-up the circuit analysis of DAC failures, using Nodal Analysis and Thevenin’s Theorem to calculate the DAC output, and model the failure on the cause of the DAC Offset Voltage failure. A Segmented DAC Offset Voltage Calculator was created to easily determine the fault coming from a PMOS Threshold Voltage (Vth) shift or a resistance mismatch of the resistor network. Circuit Simulation validated the calculated values from the DAC Offset Voltage Calculator. Nine (9) case studies were done to validate the calculated data with respect to the simulation data.