Product Yield, Test and Diagnostics - Debug Methodology for Resolving Reset Failures in Chipset Using Optical and Physical Probing Techniques
Product Yield, Test and Diagnostics - Debug Methodology for Resolving Reset Failures in Chipset Using Optical and Physical Probing Techniques
Wednesday, November 19, 2025
Summary:
With the tremendous growth of design complexity coupled with the diminishing time-to-market duration, the chances of bugs escaping into the first fabricated silicon is getting higher. Design-for-debug capability is then crucial to identify the root cause of the bugs to get fixes intercepted timely. However, when the debug capability failed to gain access, all the internal signal observation will be blocked thus poses debug challenges. This paper presents a debug methodology performed on a silicon issue with more than 10% yield loss on chipset where the hardware-based authentication failed and blocked all Design-For-X capability. This debug is performed on tester with optical/physical probing capability that pinpointed the issue to damaged fuse array and voltage level monitoring (VM) which causes the fuse sensing to fail. The root cause of this issue together with the design fix incorporated in the next silicon stepping are also discussed in this paper.
With the tremendous growth of design complexity coupled with the diminishing time-to-market duration, the chances of bugs escaping into the first fabricated silicon is getting higher. Design-for-debug capability is then crucial to identify the root cause of the bugs to get fixes intercepted timely. However, when the debug capability failed to gain access, all the internal signal observation will be blocked thus poses debug challenges. This paper presents a debug methodology performed on a silicon issue with more than 10% yield loss on chipset where the hardware-based authentication failed and blocked all Design-For-X capability. This debug is performed on tester with optical/physical probing capability that pinpointed the issue to damaged fuse array and voltage level monitoring (VM) which causes the fuse sensing to fail. The root cause of this issue together with the design fix incorporated in the next silicon stepping are also discussed in this paper.