Die Level Fault Isolation - 3D VNAND Fault Isolation Method using Lock-In OBIRCH
Die Level Fault Isolation - 3D VNAND Fault Isolation Method using Lock-In OBIRCH
Wednesday, November 19, 2025
Summary:
To increase yield and cost competitiveness, FLASH memory device developed vertical stack 3D-VNAND. Furthermore, we introduced Cell over Peripheral (COP), which places peripheral circuits, which were previously located at the same level as memory cells, under the memory cells, thereby reducing the chip size and increasing the number of Dies acquired per wafer. Due to such high stacking and high integration, it is becoming increasingly difficult to identify the location of failures in vertical structures. As one way to solve this problem, we investigated a depth-direction isolation method using lock-in OBIRCH (Optical Beam Induced Resistance Change). As a result, we obtained separate hot spot image results from overlapping memory cells and peripheral circuits. This paper describes these methods and their results.
To increase yield and cost competitiveness, FLASH memory device developed vertical stack 3D-VNAND. Furthermore, we introduced Cell over Peripheral (COP), which places peripheral circuits, which were previously located at the same level as memory cells, under the memory cells, thereby reducing the chip size and increasing the number of Dies acquired per wafer. Due to such high stacking and high integration, it is becoming increasingly difficult to identify the location of failures in vertical structures. As one way to solve this problem, we investigated a depth-direction isolation method using lock-in OBIRCH (Optical Beam Induced Resistance Change). As a result, we obtained separate hot spot image results from overlapping memory cells and peripheral circuits. This paper describes these methods and their results.