Novel looping methodology for Laser Voltage Probing of stuck-at and at-speed fails in SSN architecture
Novel looping methodology for Laser Voltage Probing of stuck-at and at-speed fails in SSN architecture
Monday, November 17, 2025: 11:50 AM
3 (Pasadena Convention Center)
Summary:
Streaming Scanning Network (SSN) is a new Design for Test (DFT) architecture that addresses the testing challenges of complex integrated circuits by enabling concurrent testing of multiple cores with limited Input/Outputs (IOs), ensuring reduced test times, simplifying physical design, and timing challenges. SSN architecture also poses major challenges for Laser Voltage Probing (LVP) and Soft Defect Localization (SDL) for at-speed and stuck-at tests. The loop setup strategies that work for older DFT architectures are no longer applicable for SSN based products. We present a unique solution in which we use retargeted looping patterns specific to failure in a particular IP and utilize chip internal signals as the trigger for LVP. Our LVP loop consists of 1000x consecutive load, capture, unload events followed by SSN End while our SDL loop consists of one load, capture and unload event followed by SSN END. Our approach has helped us achieve LVP looping efficiency of >95%, reduction in dynamic power consumption by >80% and improve LVP loop speed by 3x compared to looping constructs used in previous DFT architecture for a similar IP. We also demonstrate enabling SDL looping using chip internal signal rather than ATE for pixel clock and pass or fail decisions, which improved SDL speed by ~9x for the use case.
Streaming Scanning Network (SSN) is a new Design for Test (DFT) architecture that addresses the testing challenges of complex integrated circuits by enabling concurrent testing of multiple cores with limited Input/Outputs (IOs), ensuring reduced test times, simplifying physical design, and timing challenges. SSN architecture also poses major challenges for Laser Voltage Probing (LVP) and Soft Defect Localization (SDL) for at-speed and stuck-at tests. The loop setup strategies that work for older DFT architectures are no longer applicable for SSN based products. We present a unique solution in which we use retargeted looping patterns specific to failure in a particular IP and utilize chip internal signals as the trigger for LVP. Our LVP loop consists of 1000x consecutive load, capture, unload events followed by SSN End while our SDL loop consists of one load, capture and unload event followed by SSN END. Our approach has helped us achieve LVP looping efficiency of >95%, reduction in dynamic power consumption by >80% and improve LVP loop speed by 3x compared to looping constructs used in previous DFT architecture for a similar IP. We also demonstrate enabling SDL looping using chip internal signal rather than ATE for pixel clock and pass or fail decisions, which improved SDL speed by ~9x for the use case.