Package-level circuit editing of Copper Technology WLP Devices using PFIB
Package-level circuit editing of Copper Technology WLP Devices using PFIB
Monday, November 17, 2025: 4:00 PM
1 (Pasadena Convention Center)
Summary:
Wafer level packaging has emerged as an advanced packaging technique due to its size and lower cost compared to other packaging. Due to the thick polymer layer found on the die, conventional circuit editing has been a challenge. Accessing the top side of the die needs milling of the thick organic layer covering it. The Focused Ion Beam (FIB) is known to be a powerful tool in performing circuit editing (FIB-CE) and delayering, etching of materials, isolation and disconnection of metal interconnects. Recent years saw the emergence of the Plasma FIB (PFIB) with faster and more precise milling. In this study, the PFIB is utilized for package level circuit editing of devices in WLP with copper metallization. Results showed that the PFIB was able to etch top-down through polymer layers with O2 precursor and use Dx gas chemistry to delayer and cut copper metal interconnects in the lower layers, accomplishing design simulations and keeping the packaging intact.
Wafer level packaging has emerged as an advanced packaging technique due to its size and lower cost compared to other packaging. Due to the thick polymer layer found on the die, conventional circuit editing has been a challenge. Accessing the top side of the die needs milling of the thick organic layer covering it. The Focused Ion Beam (FIB) is known to be a powerful tool in performing circuit editing (FIB-CE) and delayering, etching of materials, isolation and disconnection of metal interconnects. Recent years saw the emergence of the Plasma FIB (PFIB) with faster and more precise milling. In this study, the PFIB is utilized for package level circuit editing of devices in WLP with copper metallization. Results showed that the PFIB was able to etch top-down through polymer layers with O2 precursor and use Dx gas chemistry to delayer and cut copper metal interconnects in the lower layers, accomplishing design simulations and keeping the packaging intact.