ISTFA Keynote Speaker: Dr. Raja Swaminathan, Corporate Vice President of Heterogenous Integration Technologies, AMD

Tuesday, November 18, 2025: 8:30 AM-9:30 AM
Pasadena Convention Center
Future of AI Hardware Enabled by Advanced Packaging

Chiplet architectures are fundamental to the continued economic viable growth of power efficiency of AI hardware and edge computing. The slowing of Moore’s law has also placed advanced packaging at the critical juncture of technology-architecture intersection driving unique product capabilities. New heterogeneous architectures like 2.5D architectures and 3D Hybrid bonded architectures driving AMD’s industry leading advanced technology roadmap to enable power, performance, area, and cost (PPAC) will be discussed. Other topics including Chiplets for AI, challenges and solutions for large chiplet modules etc. will also be discussed.

Biography: Dr. Raja Swaminathan is the Corporate Vice President of Packaging at AMD, spearheading the development of AMD’s advanced packaging and heterogeneous integration roadmap. With a distinguished career spanning roles at Intel, Apple, and now AMD, Dr. Swaminathan’s expertise in design-technology co-optimization and dedication to optimizing power, performance, area, and cost (PPAC) have led to significant technological advancements such as EMIB, Apple’s Mx packages, 3D V-Cache, and 3.5D architectures for AI accelerators. Dr. Swaminathan holds a PhD from Carnegie Mellon University and an undergraduate degree from IIT Madras. With over 100 patents and more than 40 published papers to their name, Dr. Swaminathan was recently recognized as an IEEE Fellow and serves as a technical advisor to multiple startups. His unwavering commitment to heterogeneous integration continues to drive the boundaries of silicon technology. He also shares his insights on life and leadership, drawing lessons from the semiconductor industry, on his LinkedIn profile.
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