Application of fault localization emission techniques to cases of Copper Re-Distribution Layer VIAS delamination
Application of fault localization emission techniques to cases of Copper Re-Distribution Layer VIAS delamination
Wednesday, October 7, 2026: 10:40 AM
Summary:
Performing the Failure Analysis (FA) of an electrical failure consequence of a back-end issue, may turn out in an extremely challenging task: standard localization techniques are well working on both silicon defects and silicon damages, while they are showing some limitations when the root cause of the device malfunction must be found in the connectivity structure. The difficulty increases when the involved structure is the top level of connection, on the other side of silicon back-side, in a context of possible active components related failure. The cases described in this work are referring to different devices in Wafer Level Chip Scale Package (WLCSP). The failing devices were collected during their qualification flow: accelerated aging tests, both biased and unbiased Highly Accelerated Stress Test (bHAST and uHAST respectively) generated rejects with nonspecific macro failure modes. In this paper it is described the characterization of electrical symptoms observed at reliability verification test read points. The centre of the work is then dedicated to the application of the techniques available in the hands of Failure Analysis team to the localization phase and the obtained results: electrical characterization as first and crucial input (the only input in some cases), Lock-in thermography and Light Emission Microscopy. Lastly some examples of the physical analysis flow by mean of Focused Ion Beam (FIB) x-sections, Transmission Electron Microscopy (TEM) and Electron Dispersion X-Ray Spectroscopy (EDX) elemental analysis is added.
Performing the Failure Analysis (FA) of an electrical failure consequence of a back-end issue, may turn out in an extremely challenging task: standard localization techniques are well working on both silicon defects and silicon damages, while they are showing some limitations when the root cause of the device malfunction must be found in the connectivity structure. The difficulty increases when the involved structure is the top level of connection, on the other side of silicon back-side, in a context of possible active components related failure. The cases described in this work are referring to different devices in Wafer Level Chip Scale Package (WLCSP). The failing devices were collected during their qualification flow: accelerated aging tests, both biased and unbiased Highly Accelerated Stress Test (bHAST and uHAST respectively) generated rejects with nonspecific macro failure modes. In this paper it is described the characterization of electrical symptoms observed at reliability verification test read points. The centre of the work is then dedicated to the application of the techniques available in the hands of Failure Analysis team to the localization phase and the obtained results: electrical characterization as first and crucial input (the only input in some cases), Lock-in thermography and Light Emission Microscopy. Lastly some examples of the physical analysis flow by mean of Focused Ion Beam (FIB) x-sections, Transmission Electron Microscopy (TEM) and Electron Dispersion X-Ray Spectroscopy (EDX) elemental analysis is added.