A Direct Backside Approach Failure Analysis in High-Layer-Count 3D Flash Memory for High Resistance Failures
A Direct Backside Approach Failure Analysis in High-Layer-Count 3D Flash Memory for High Resistance Failures
Wednesday, October 7, 2026: 4:20 PM
Summary:
As 3D flash devices continue to scale to higher layer counts and adopt CMOS‑under‑Array (CuA) or CMOS Directly Bonded to Array (CBA) architectures, traditional frontside failure analysis becomes increasingly limited by deep, high‑aspect‑ratio stacks that obscure buried defects. This work presents a direct backside delayering methodology that creates a physical access path to the deeply embedded CMOS logic responsible for high‑resistance failures in advanced 3D NAND. The workflow integrates frontside layout‑aligned FIB through‑silicon fiducial marking with infrared microscopy to precisely map electrical coordinates to the backside surface, enabling accurate localization and controlled substrate thinning. Subsequent backside grinding and SEM passive voltage contrast successfully identified a dark‑contrast discontinuity corresponding to an electrically floating metal segment. Final TEM characterization confirmed a malformed via and partial metal voiding at the M0–V1 interface as the root cause. This backside‑first approach reduces turnaround time by ~30% and significantly improves analysis success for buried defects in next‑generation NAND technologies.
As 3D flash devices continue to scale to higher layer counts and adopt CMOS‑under‑Array (CuA) or CMOS Directly Bonded to Array (CBA) architectures, traditional frontside failure analysis becomes increasingly limited by deep, high‑aspect‑ratio stacks that obscure buried defects. This work presents a direct backside delayering methodology that creates a physical access path to the deeply embedded CMOS logic responsible for high‑resistance failures in advanced 3D NAND. The workflow integrates frontside layout‑aligned FIB through‑silicon fiducial marking with infrared microscopy to precisely map electrical coordinates to the backside surface, enabling accurate localization and controlled substrate thinning. Subsequent backside grinding and SEM passive voltage contrast successfully identified a dark‑contrast discontinuity corresponding to an electrically floating metal segment. Final TEM characterization confirmed a malformed via and partial metal voiding at the M0–V1 interface as the root cause. This backside‑first approach reduces turnaround time by ~30% and significantly improves analysis success for buried defects in next‑generation NAND technologies.