Bridging a Gap between Physical and Electrical Failure Analysis: Fault Localization on TEM Lamellae Enabled by Workflow Redesign and optional Probing Pads
Bridging a Gap between Physical and Electrical Failure Analysis: Fault Localization on TEM Lamellae Enabled by Workflow Redesign and optional Probing Pads
Tuesday, October 6, 2026: 11:30 AM
Summary:
Continued scaling and increasing three‑dimensional complexity of advanced CMOS technologies, including FinFET and Gate All Around (GAA) devices, have created a widening gap between electrical and physical failure analysis. Subtle defects such as fin nano‑cracks, dopant variations, interface traps and resistive anomalies may produce clear electrical signatures while remaining extremely difficult to capture using conventional TEM-based workflows. A persistent limitation in these workflows is the loss of electrical access once a TEM lamella is extracted, preventing further fault localization and forcing analysts to rely solely on diffraction or material contrast and the related TEM spectroscopy techniques. This is often far removed from the original electrical evidence, which in most cases was gathered in another plane; top-down versus cross-section. This work introduces a redesigned TEM preparation methodology that keeps full electrical accessibility to both planar view and cross‑section TEM lamellae. By replacing the initial deposition material from a conductive material (e.g. platinum, tungsten, carbon, etc.) with an isolating dielectric, selected areas of the top-down structure remain electrically isolated after lift-out and attachment to a TEM grid. The final protective layer can still be used as before on top of the insulating dielectric. As a result, complete device‑level measurements can be performed on the TEM lamella after lift‑out, optionally assisted by FIB‑fabricated probe pads for out-of-plane contacting. The approach is compatible with advanced preparation flows, including high‑precision end-pointing, and enables correlation of nanoprobing, e-beam localization and TEM material analysis within the same physical sample. Multiple case studies demonstrate the capabilities of this method, including planar view defect localization, cross-section view P‑N junction mapping and full device characterization. FIB-fabricated probe pads introduce a series resistance which must be considered, for example in contact resistance investigations. Implantations from Ga-FIB can significantly increase leakage and impact overall transistor curves which needs to be taken into account. The present results can significantly enhance the precision and efficiency of root‑cause identifications. This establishes a semi-reversible link between electrical and physical failure analysis, where TEM lamella preparation was historically the final step of the FA flow. Moreover, this approach becomes particularly relevant for advanced architectures such as backside power delivery networks and 3D stacked devices, where optical fault isolation techniques lose line-of-sight access. By enabling electrical probing directly on TEM lamellae, the method provides an alternative pathway for defect localization in otherwise inaccessible geometries, helping to close the gap between electrical and physical failure analysis in advanced CMOS technologies.
Continued scaling and increasing three‑dimensional complexity of advanced CMOS technologies, including FinFET and Gate All Around (GAA) devices, have created a widening gap between electrical and physical failure analysis. Subtle defects such as fin nano‑cracks, dopant variations, interface traps and resistive anomalies may produce clear electrical signatures while remaining extremely difficult to capture using conventional TEM-based workflows. A persistent limitation in these workflows is the loss of electrical access once a TEM lamella is extracted, preventing further fault localization and forcing analysts to rely solely on diffraction or material contrast and the related TEM spectroscopy techniques. This is often far removed from the original electrical evidence, which in most cases was gathered in another plane; top-down versus cross-section. This work introduces a redesigned TEM preparation methodology that keeps full electrical accessibility to both planar view and cross‑section TEM lamellae. By replacing the initial deposition material from a conductive material (e.g. platinum, tungsten, carbon, etc.) with an isolating dielectric, selected areas of the top-down structure remain electrically isolated after lift-out and attachment to a TEM grid. The final protective layer can still be used as before on top of the insulating dielectric. As a result, complete device‑level measurements can be performed on the TEM lamella after lift‑out, optionally assisted by FIB‑fabricated probe pads for out-of-plane contacting. The approach is compatible with advanced preparation flows, including high‑precision end-pointing, and enables correlation of nanoprobing, e-beam localization and TEM material analysis within the same physical sample. Multiple case studies demonstrate the capabilities of this method, including planar view defect localization, cross-section view P‑N junction mapping and full device characterization. FIB-fabricated probe pads introduce a series resistance which must be considered, for example in contact resistance investigations. Implantations from Ga-FIB can significantly increase leakage and impact overall transistor curves which needs to be taken into account. The present results can significantly enhance the precision and efficiency of root‑cause identifications. This establishes a semi-reversible link between electrical and physical failure analysis, where TEM lamella preparation was historically the final step of the FA flow. Moreover, this approach becomes particularly relevant for advanced architectures such as backside power delivery networks and 3D stacked devices, where optical fault isolation techniques lose line-of-sight access. By enabling electrical probing directly on TEM lamellae, the method provides an alternative pathway for defect localization in otherwise inaccessible geometries, helping to close the gap between electrical and physical failure analysis in advanced CMOS technologies.