Resolving Open Metal Line Defects Driving Logic Emission in a 90-nm Copper based Process Technology using SEM-based Localization and Circuit Analysis
Resolving Open Metal Line Defects Driving Logic Emission in a 90-nm Copper based Process Technology using SEM-based Localization and Circuit Analysis
Tuesday, October 6, 2026: 3:20 PM
Summary:
This paper presents a methodical failure analysis approach for a 90-nm copper-based process technology device, incorporating circuit analysis based on Photon Emission Microscopy (PEM) results, Passive Voltage Contrast (PVC) analysis, and nanoprobe-based Electron Beam Absorbed Current (EBAC) techniques. Conventional failure analysis workflows, such as probe pad deposition and micro-probing, often induce physical damage or alter electrical behavior, compromising test integrity, leading to inconclusive results, and hiding the true root cause. These limitations are especially pronounced in 90 nm copper-based process technology, where the fragility of the passivation and interconnect structures increases the likelihood of sample damage. The proposed methodology successfully resolved previously inconclusive cases and enabled the isolation of fabrication-related open metal line defects responsible for logic-gate emission signatures and associated system-level failures.
This paper presents a methodical failure analysis approach for a 90-nm copper-based process technology device, incorporating circuit analysis based on Photon Emission Microscopy (PEM) results, Passive Voltage Contrast (PVC) analysis, and nanoprobe-based Electron Beam Absorbed Current (EBAC) techniques. Conventional failure analysis workflows, such as probe pad deposition and micro-probing, often induce physical damage or alter electrical behavior, compromising test integrity, leading to inconclusive results, and hiding the true root cause. These limitations are especially pronounced in 90 nm copper-based process technology, where the fragility of the passivation and interconnect structures increases the likelihood of sample damage. The proposed methodology successfully resolved previously inconclusive cases and enabled the isolation of fabrication-related open metal line defects responsible for logic-gate emission signatures and associated system-level failures.