Integrated PFIB Delayering and In-Situ AFM-Based Electrical Characterization for Rapid, Site-Specific 3D Failure Analysis of Advanced-Node Devices
Integrated PFIB Delayering and In-Situ AFM-Based Electrical Characterization for Rapid, Site-Specific 3D Failure Analysis of Advanced-Node Devices
Tuesday, October 6, 2026: 3:20 PM
Summary:
This work presents an integrated in-situ workflow combining plasma focused ion beam (PFIB) delayering with atomic force microscopy (AFM)-based electrical characterization for advanced semiconductor failure analysis. Conventional approaches relying on ex-situ sample transfer suffer from surface degradation, repeated region-of-interest (ROI) localization, and limited throughput. By integrating AFM directly within a SEM-PFIB platform, the proposed method enables sequential, layer-by-layer analysis within a single vacuum environment, preserving surface integrity and maintaining precise spatial correlation across layers. The workflow was demonstrated on a 5 nm logic device, where interconnect, via, contact, and transistor-level structures were accessed through controlled PFIB delayering and analyzed using conductive AFM (C-AFM). High-resolution electrical maps reveal nanoscale features relevant to failure mechanisms, while SEM-guided navigation enables site-specific targeting of critical regions. The approach significantly improves efficiency, with combined delayering and measurement times of approximately 20–25 minutes per layer. Additionally, electron-beam-assisted C-AFM (EBC-AFM) is implemented to enable electrical characterization without physical back-contact, extending applicability to electrically isolated structures. This methodology provides a practical pathway for rapid, high-resolution, three-dimensional electrical failure analysis of advanced-node semiconductor devices.
This work presents an integrated in-situ workflow combining plasma focused ion beam (PFIB) delayering with atomic force microscopy (AFM)-based electrical characterization for advanced semiconductor failure analysis. Conventional approaches relying on ex-situ sample transfer suffer from surface degradation, repeated region-of-interest (ROI) localization, and limited throughput. By integrating AFM directly within a SEM-PFIB platform, the proposed method enables sequential, layer-by-layer analysis within a single vacuum environment, preserving surface integrity and maintaining precise spatial correlation across layers. The workflow was demonstrated on a 5 nm logic device, where interconnect, via, contact, and transistor-level structures were accessed through controlled PFIB delayering and analyzed using conductive AFM (C-AFM). High-resolution electrical maps reveal nanoscale features relevant to failure mechanisms, while SEM-guided navigation enables site-specific targeting of critical regions. The approach significantly improves efficiency, with combined delayering and measurement times of approximately 20–25 minutes per layer. Additionally, electron-beam-assisted C-AFM (EBC-AFM) is implemented to enable electrical characterization without physical back-contact, extending applicability to electrically isolated structures. This methodology provides a practical pathway for rapid, high-resolution, three-dimensional electrical failure analysis of advanced-node semiconductor devices.