Analytical Approach for Revealing Latent Intermittent Column Failures Associated with Bit-Line Sense Amplifier Vulnerability in DRAM
Analytical Approach for Revealing Latent Intermittent Column Failures Associated with Bit-Line Sense Amplifier Vulnerability in DRAM
Tuesday, October 6, 2026: 10:10 AM
Summary:
Intermittent column failures in high-density DRAM are investigated to elucidate their underlying physical mechanism. Comprehensive electrical characterization revealed that failing DRAM chips consistently exhibit relatively low threshold voltages (Vt) in the bit-line sense amplifier transistors, which markedly increase their susceptibility to sub-threshold leakage currents. However, this vulnerability can remain hidden due to circuit-level bit-line compensation, making it difficult to detect and screen using conventional analysis methods. To expose the concealed mechanism, multi-factor analytical conditions are devised that deliberately minimize the bit-line differential voltage (ΔVBL) by combining elevated temperature, prolonged retention time, and a controlled delay in sensing interval (t_DS). Under these conditions, the failure behavior of the low-Vt group, previously indistinguishable from that of the reference group, becomes clearly separated. In particular, extending t_DS demonstrates the progressive degradation of ΔVBL induced by leakage, ultimately leading to functional sensing failure. These results confirm that the proposed methodology effectively unmasks hidden column-failure mechanisms and provides a robust, product-level failure analysis framework for identifying root causes in advanced DRAM technologies.
Intermittent column failures in high-density DRAM are investigated to elucidate their underlying physical mechanism. Comprehensive electrical characterization revealed that failing DRAM chips consistently exhibit relatively low threshold voltages (Vt) in the bit-line sense amplifier transistors, which markedly increase their susceptibility to sub-threshold leakage currents. However, this vulnerability can remain hidden due to circuit-level bit-line compensation, making it difficult to detect and screen using conventional analysis methods. To expose the concealed mechanism, multi-factor analytical conditions are devised that deliberately minimize the bit-line differential voltage (ΔVBL) by combining elevated temperature, prolonged retention time, and a controlled delay in sensing interval (t_DS). Under these conditions, the failure behavior of the low-Vt group, previously indistinguishable from that of the reference group, becomes clearly separated. In particular, extending t_DS demonstrates the progressive degradation of ΔVBL induced by leakage, ultimately leading to functional sensing failure. These results confirm that the proposed methodology effectively unmasks hidden column-failure mechanisms and provides a robust, product-level failure analysis framework for identifying root causes in advanced DRAM technologies.