Study on Characteristic Degradation Induced by Unused Dummy Patterns in Open Bitline DRAM

Summary:

To shrink the chip area, an open bitline architecture has been adopted in commercial DRAM, which inevitably creates unused dummy patterning regions. The dummy bitlines in these regions are left either floating or biasing state, according to the original purpose of design. During mass production of sub‑20 nm DRAM, a critical reliability issue emerged in the floating dummy bitlines. Leakage currents of adjacent transistors cause a gradual voltage decay on the floating lines. The resulting Lateral Body Effect raises the threshold voltage of neighboring cell transistors, thereby degrading the write recovery time characteristics of adjacent memory cells. In this study, we systematically elucidate the underlying mechanism of this phenomenon and propose a novel circuit scheme that dynamically adjusts the dummy bitline bias in synchrony with the Active command. The proposed methodology achieves power savings while minimizing performance degradation.