Optimizing X-ray laminography for planar semiconductor devices: A CMOS camera sensor case study
Optimizing X-ray laminography for planar semiconductor devices: A CMOS camera sensor case study
Thursday, October 8, 2026: 10:40 AM
Summary:
This study investigates optimization of X-ray laminography scan parameters for fast, high-quality inspection of planar semiconductor devices using a CMOS camera sensor with through-silicon vias (TSVs) as a case study. By varying exposure time, projection count, X-ray spot size, and voltage, trade-offs between scan time, resolution, and image quality were analyzed. Results demonstrate that smaller X-ray spots improve resolution but require longer scans, while fewer projections reduce quality and introduce artifacts. The findings provide practical guidance for balancing throughput and detail in nondestructive 3D imaging of advanced semiconductor packaging.
This study investigates optimization of X-ray laminography scan parameters for fast, high-quality inspection of planar semiconductor devices using a CMOS camera sensor with through-silicon vias (TSVs) as a case study. By varying exposure time, projection count, X-ray spot size, and voltage, trade-offs between scan time, resolution, and image quality were analyzed. Results demonstrate that smaller X-ray spots improve resolution but require longer scans, while fewer projections reduce quality and introduce artifacts. The findings provide practical guidance for balancing throughput and detail in nondestructive 3D imaging of advanced semiconductor packaging.