Enabling High-Resolution AFM Analysis of Advanced Semiconductor Devices through Concentrated Argon Ion Beam Milling
Enabling High-Resolution AFM Analysis of Advanced Semiconductor Devices through Concentrated Argon Ion Beam Milling
Thursday, October 8, 2026: 10:40 AM
Bridge Hall (Henry B. González Convention Center)
Summary:
Standard Ga-FIB (Ga-Focused Ion Beam) preparation introduces surface amorphization, curtaining, and conductive Ga-ion implantation. In sub-10 nm semiconductor nodes, these artifacts severely mask intrinsic device signals during high-resolution Atomic Force Microscopy (AFM) electrical analysis. To overcome this limitation, a novel dual-beam specimen preparation framework integrates high-throughput Ga-FIB milling with a low-energy, concentrated Ar-ion beam finishing step. Validated on a commercial 7 nm FinFET node, this optimized workflow preserves fragile transistor architectures while drastically mitigating surface artifacts. The low-energy Ar-ion polish reduces surface roughness to a sub-nanometer scale (50 nm). By eliminating the amorphous and Ga-implanted layers, this methodology ensures a highly stable tip-sample electrical contact. Consequently, conductive-AFM (C-AFM) can accurately resolve the true electrical properties of the device that were previously obscured. Ultimately, this reliable preparation workflow can be successfully extended to advanced AFM modes, enabling high-resolution subsurface doping contrast in next-generation semiconductor nodes.
Standard Ga-FIB (Ga-Focused Ion Beam) preparation introduces surface amorphization, curtaining, and conductive Ga-ion implantation. In sub-10 nm semiconductor nodes, these artifacts severely mask intrinsic device signals during high-resolution Atomic Force Microscopy (AFM) electrical analysis. To overcome this limitation, a novel dual-beam specimen preparation framework integrates high-throughput Ga-FIB milling with a low-energy, concentrated Ar-ion beam finishing step. Validated on a commercial 7 nm FinFET node, this optimized workflow preserves fragile transistor architectures while drastically mitigating surface artifacts. The low-energy Ar-ion polish reduces surface roughness to a sub-nanometer scale (50 nm). By eliminating the amorphous and Ga-implanted layers, this methodology ensures a highly stable tip-sample electrical contact. Consequently, conductive-AFM (C-AFM) can accurately resolve the true electrical properties of the device that were previously obscured. Ultimately, this reliable preparation workflow can be successfully extended to advanced AFM modes, enabling high-resolution subsurface doping contrast in next-generation semiconductor nodes.