Automated Workflow for High-Precision Delayering and Failure Analysis in 7nm Programmable Logic
Automated Workflow for High-Precision Delayering and Failure Analysis in 7nm Programmable Logic
Wednesday, October 7, 2026: 8:40 PM
Summary:
As logic process technology advances, precise physical failure analysis and deprocessing are increasingly vital especially in electrical probing sample preparation and passive voltage contrast (PVC) application. This work introduces an automated workflow for sample delayering, imaging, and probing preparation using the Xe source PFIB platform, optimizing the process for 7nm programmable logic devices. By tuning recipe variables and integrating adaptive end pointing, the workflow accurately identifies metal and via layers in real time. A robust ROI targeting method using fiducials ensures precise milling. The unified automation reduces manual effort, enhances reproducibility, and accelerates data acquisition, providing a scalable solution for advanced semiconductor failure analysis.
As logic process technology advances, precise physical failure analysis and deprocessing are increasingly vital especially in electrical probing sample preparation and passive voltage contrast (PVC) application. This work introduces an automated workflow for sample delayering, imaging, and probing preparation using the Xe source PFIB platform, optimizing the process for 7nm programmable logic devices. By tuning recipe variables and integrating adaptive end pointing, the workflow accurately identifies metal and via layers in real time. A robust ROI targeting method using fiducials ensures precise milling. The unified automation reduces manual effort, enhances reproducibility, and accelerates data acquisition, providing a scalable solution for advanced semiconductor failure analysis.