Failure analysis methods to localize defects in data path on 3D Flash memory products
Failure analysis methods to localize defects in data path on 3D Flash memory products
Wednesday, October 7, 2026: 1:40 AM
Summary:
For 3D Flash memory products, competitiveness depends not only on die size but also on how quickly data can be programmed into and read from the memory cells. Achieving high performance requires minimizing delay throughout the entire data path—from the I/O interface, through buffers and sense amplifiers, to the memory array itself. As data path speeds continue to increase, failure analysis of the associated circuits becomes increasingly challenging. In this paper, we examine several analytical techniques used to identify root cause defects within the NAND data path.
For 3D Flash memory products, competitiveness depends not only on die size but also on how quickly data can be programmed into and read from the memory cells. Achieving high performance requires minimizing delay throughout the entire data path—from the I/O interface, through buffers and sense amplifiers, to the memory array itself. As data path speeds continue to increase, failure analysis of the associated circuits becomes increasingly challenging. In this paper, we examine several analytical techniques used to identify root cause defects within the NAND data path.