Gate Oxide rupture isolation using Electron Beam absorbed Current (EBAC) technique on a 22nm device
Gate Oxide rupture isolation using Electron Beam absorbed Current (EBAC) technique on a 22nm device
Tuesday, October 6, 2026: 10:50 AM
Summary:
One of the defects which are very time consuming to capture is a gate oxide breakdown defects on big transistors or capacitors. Typical process for a suspect gate oxide defect involves Electrical Fault Isolation (EFA) of the failure to a particular or a group of transistors, capacitors followed by de-processing and checking passive voltage contrast (PVC). When PVC observes an anomalous VC, failure may be further confirmed by either nano probing or conductive AFM and measuring the leakage. Once the failure/leakage is confirmed on a particular gate, FA engineers typically proceed with cross section of the leaky gate, backside SEM inspection (after Si and oxide etch to decorate the poly gate), or top-down SEM inspection . But there are some limitations and disadvantages to these techniques. Cross sectioning is very time consuming and there is always a chance of missing the defect, particularly if the gates/capacitor plate are noticeably big. SEM images showing oxide defects by delayering (especially topside) will always be challenged against the artifacts caused by delayering the sample. Further isolating the failure to a particular part of the gate/capacitor plate would be extremely helpful in these scenarios. Even though there has been some theoretical literature on isolating gate oxide defects, there is minimal or no published literature showing gate oxide defects isolated using EBAC/EBIC [5]. In this paper, we present a case study where a gate oxide rupture is successfully isolated using EBAC/EBIC technique on a 22nm device.
One of the defects which are very time consuming to capture is a gate oxide breakdown defects on big transistors or capacitors. Typical process for a suspect gate oxide defect involves Electrical Fault Isolation (EFA) of the failure to a particular or a group of transistors, capacitors followed by de-processing and checking passive voltage contrast (PVC). When PVC observes an anomalous VC, failure may be further confirmed by either nano probing or conductive AFM and measuring the leakage. Once the failure/leakage is confirmed on a particular gate, FA engineers typically proceed with cross section of the leaky gate, backside SEM inspection (after Si and oxide etch to decorate the poly gate), or top-down SEM inspection . But there are some limitations and disadvantages to these techniques. Cross sectioning is very time consuming and there is always a chance of missing the defect, particularly if the gates/capacitor plate are noticeably big. SEM images showing oxide defects by delayering (especially topside) will always be challenged against the artifacts caused by delayering the sample. Further isolating the failure to a particular part of the gate/capacitor plate would be extremely helpful in these scenarios. Even though there has been some theoretical literature on isolating gate oxide defects, there is minimal or no published literature showing gate oxide defects isolated using EBAC/EBIC [5]. In this paper, we present a case study where a gate oxide rupture is successfully isolated using EBAC/EBIC technique on a 22nm device.