Panel Discussion: Design for Analysis: Confronting the Challenges of Backside Power, Heterogeneous Integration, and Co-Packaged Optics in the AI Era
Panel Discussion: Design for Analysis: Confronting the Challenges of Backside Power, Heterogeneous Integration, and Co-Packaged Optics in the AI Era
Wednesday, October 7, 2026: 1:30 PM-3:00 PM
Exhibit Hall - Industry Forum (Henry B. González Convention Center)
Design for Analysis: Confronting the Challenges of Backside Power, Heterogeneous Integration, and Co-Packaged Optics in the AI EraWednesday, October 7, 2026 | 1:30 – 3:00 p.m.
Join us for an interactive session with industry experts on the FA challenges posed by these disruptive technologies. Their accelerated adoption, driven primarily by the insatiable demands of AI, have created glaring gaps in all aspects of failure analysis, including test/diagnosis, EFI/EFA, sample prep, and PFA. Design changes at the chip, toolset, and workflow levels are desperately needed as the semiconductor industry charges towards $1T revenue. Our panel of experts from AMD, Carl Zeiss, IMEC, NVIDIA, and TSMC will share their perspectives on the requirements and roadblocks to meeting these challenges in what should prove to be a lively discussion.
See more of: Technical Program