Panel Discussion: Design for Analysis: Confronting the Challenges of Backside Power, Heterogeneous Integration, and Co-Packaged Optics in the AI Era
Wednesday, October 7, 2026 | 1:30 – 3:00 p.m.
An interactive session with a panel of industry experts to discuss the failure analysis challenges posed by these disruptive technologies.
Moderators
Dr. Venkat-Krishnan Ravikumar, Advanced Micro Devices
Dr. William Lo, NVIDIA
Panelists
Deepak Goyal, ZEISS
Biography: Deepak Goyal graduated with a PhD from State University of New York, Stony Brook. He is currently working at Carl Zeiss in the Advanced Packaging Product Strategy team. He has retired from Intel as Sr.Principal Engineer/Sr. Director, leading the Global Assembly and Test (Technology Development and Manufacturing) Failure/Yield Analysis Labs. He has helped with the development of all Intel assembly technologies including FCxGA, FCCSP, TSVs, POINT, EMIB, co-EMIB and Foveros. He is an expert in the defect characterization, failure analysis and failure mechanism understanding for packages and advanced analytical metrologies development. He has taught Professional Development courses on Package FA/FI methods and failure mechanisms at the Electronics Components and Technology Conference (ECTC). Deepak has authored and co-authored over 60 papers and holds 19 US patents. He has co-authored 2 book chapters and has co-edited 2 books on “3D Microelectronic Packaging”. He is an IEEE Fellow and an EPS Distinguished Lecturer.
Jeff Rearick, AMD
Biography: Jeff Rearick is a Senior Fellow at AMD. He has been with AMD for 18 years and leads the DFX Strategy team, whose mission is to look just far enough into the future of test and debug and validation to keep a steady stream of innovations coming down the pipeline to intercept ever-advancing AMD products. Jeff is a member of the International Test Conference Steering Committee, served as ITC Program Chair in 2023, has served on Program Committee for the European Test Symposium, is a longstanding member of the IEEE Test Technology Standards Committee, and is currently the Editor for three IEEE working groups (IEEE 1687, P1687.1, and P1687.2). Prior to joining AMD, he did test engineering and DFT design at Hewlett-Packard and Agilent Technologies for 22 years. He holds BSEE and MSEE degrees from Purdue University and the University of Illinois, respectively.
Rudolf Schlangen, NVIDIA
Biography: Rudolf Schlangen began his career at Siemens in Düsseldorf as a Telcom‑Electronics Technician, where he got a first glimpse at system‑level failure analysis. He earned his MS in Electrical Engineering from the University of Duisburg in 2004 before joining Prof. Christian Boit’s group at the Technical University of Berlin. His research focused on FIB‑backside circuit editing and the impact of FIB thinning down to the transistor‑level, including the first successful demonstration of backside e‑beam probing on FET level. After completing his PhD in 2009, Rudolf joined DCG Systems in California, leading Lock‑In Thermography applications development. He moved to Nvidia in 2012 and has been managing logic-fault‑isolation and design‑debug with teams in California and Taiwan since 2014, driving innovation in advanced FA methodologies for cutting‑edge IC technologies.
Kristof Jacobs, IMEC