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Session 19: Yield Enhancement
Location: Meeting Room J1-J2 (San Jose McEnery Convention Center)
(Please check final room assignments on-site).
Session Description: This session examines failure analysis as it relates to yield enhancement issues during wafer fabrication. Topics of examination include defect classification and correlation to test, yield improvement or assessment methodologies, process/control improvements for yield related issues, the use of test concepts to catch yield related problems, and case studies illustrating yield analysis and corrective actions.
Editor:	Ms Carol Boye IBM
Session Chair:	Ms Carol Boye IBM
9:25 AM	SYMP0519.2		Burn-In Acceleration Considerations in 130nm and 90nm Products
9:50 AM	SYMP0519.3		Statistical Evaluation of Scan Test Diagnosis Results for Yield Enhancement of Logic Designs
10:15 AM	SYMP0519.4		In-Line Voltage Contrast Inspection of Ungrounded Chain Test Structures for Timely and Detailed Characterization of Contact and Via Yield Loss
10:40 AM	SYMP0519.5		Impact of Metal Pad Etch-Induced Plasma Damage on Dynamic Retention Time Degradation during High Temperature Stress in High Density DRAM Technology
11:05 AM	SYMP0519.6		Effect of the Ash Chemistries on the TDDB Lifetime of the Cu/ULK Dielectrics