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| Session 11: Die Level Fault Isolation | ||||
| Location: Ballroom B (Renaissance Austin Hotel) | ||||
| (Please check final room assignments on-site). | ||||
| Session Description: This session includes novel investigations related to VLSI (debug, yield enhancements, field returns), as well as improvements to tools and techniques used in fault isolation not covered in other sessions. Additional information will be presented on fault isolation efficiency: technique comparison, quickness, accuracy, upstream issues (test, sample preparation, sample stimulation), downstream issues (physical analysis), and payback (usefulness of the fault isolation). | ||||
| Editor: | Dr. J. Joseph Clement Sandia National Laboratories, Albuquerque, NM | |||
| Session Chair: | Dr. J. Joseph Clement Sandia National Laboratories, Albuquerque, NM | |||
| 3:55 PM | Analysis of Delta Iddq Soft Fails on Pass Chips | |||
| 4:20 PM | Applications of Soft Defect Localization (SDL) on AMD Advanced SOI Microprocessors | |||
| 4:45 PM | Active Voltage Contrast for Failure Localization in Test Structures | |||
| 5:10 PM | Floating Substrate Passive Voltage Contrast (FSPVC) | |||
| 5:35 PM | Fault Identification by Use of a Simulated Passive Voltage Contrast Reference CAD Display | |||