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Session 3: Failure Analysis Process I
Location: Meeting Room E145 (Oregon Convention Center )
(Please check final room assignments on-site).
Session Description:
Session Chair:	Mr. David Burgess Accelerated Analysis, Half Moon Bay, CA
12:20 PM			Active Voltage Contrast and Seebeck Effect Imaging as Complementary Techniques for Localization of Resistive Interconnections
12:45 PM			A Logical Problem Solving Process for High Via Resistance Root Cause Analysis
1:10 PM			Vdd Leakage Analysis by a Combination of Various Failure Analysis Techniques
1:35 PM			Break
1:45 PM			Physical Failure Analysis Techniques and Studies on Vertical Short Issue of 65nm Devices
2:10 PM			Fast root cause analysis based on electrical defect localization
2:35 PM			Failure Analysis for Gate Oxide Breakdown
3:00 PM			Break