Failure Analysis of Bit Line to SNC Leakage Fail in 2xnm DRAM Using Nano Probing Technique

Tuesday, November 11, 2014: 11:10 AM
310 B (George R. Brown Convention Center )
Mr. Jaeho Won , SK hynix, Icheon-si, South Korea
Mr. Jundong Kim , SK hynix, Icheon-si, South Korea
Mrs. Jina Kim , SK hynix, Icheon-si, South Korea
Mrs. Jihye Shin , SK hynix, Icheon-si, South Korea
Mr. Jihoon Kim , SK hynix, Icheon-si, South Korea
Ms. Kyungrim Lee , SK hynix, Icheon-si, South Korea
Ms. Miae Yoon , SK hynix, Icheon-si, South Korea
Mr. Jong Hak Lee , SK Hynix Semiconductor Inc, Icheon-si, South Korea
Mr. Jaeyun Lee , SK Hynix Semiconductor Inc, Icheon-si, South Korea
Mr. Weonjoon Suh , SK hynix, Icheon-si, South Korea
Dr. Hyeonsoo Kim , SK hynix, Icheon-si, South Korea

Summary:

Leakage current from bit line to SNC is one of the most critical issues in DRAM operation. Such failure becomes more difficult to visualize as the device shrinkage. In thsi study, bit line to SNC leakage fail was analyzed using nano-probing tool in 2xnm DRAM technology.