Marginal Failure Diagnosed with LADA: Case Studies
Marginal Failure Diagnosed with LADA: Case Studies
Wednesday, November 12, 2014
Exhibit Hall B3 (George R. Brown Convention Center )
Summary:
During the early stage of process development, the major activities are yield up with DFT test such as Memory BIST and SCAN test. There are plenty of commercial and in-house diagnosis tools for DFT. So in case of defective failure, FA procedure is rather simple and standardized: run EDA tool, get fail location, do pFA then feedback to process engineering. But that of marginal failure is generally more complicate. Engineer should consider many different scenarios to find the root cause. The marginal voltage fail is caused from many different reasons and the analysis from marginal fail is of course very important to screen out healthy devices and also right index of both the yield concerned with process technology and the design methodology. In this paper, the author dealt with three marginal voltage fail case studies: scan chain fail, digital function fail and analog function fail. Through these case studies, LADA successfully defined the fault location and the reason of device alteration was well explained with further study. It is obvious that LADA is very effective way to analyze the marginal fail in case FA engineer doesn’t have much design information because the result is very intuitive and clear. Also it is said that there is no doubt of LADA results because the result of LADA is defined from tester and it is direct indication of changing voltage margin. The root cause of marginal voltage failures were successfully analyzed with LADA, also LVP supported to probe the signal. LADA immediately displayed suspicious location and well explained the results. From In case study 1, LADA detected an exact fault location in the F/F by exciting p-mos performance faster than normal operation at clock inverter. Finally cross section view showed anomaly on contact and poly caused from process instability.In case study 2, LADA detected hold time violation location due to design issue and helped to find out design mistake. In case study 3, it is also effective utilizing LADA not only dynamic function but also static function. But the main difference is there is only junction leakage due to electron hole pair generation.
During the early stage of process development, the major activities are yield up with DFT test such as Memory BIST and SCAN test. There are plenty of commercial and in-house diagnosis tools for DFT. So in case of defective failure, FA procedure is rather simple and standardized: run EDA tool, get fail location, do pFA then feedback to process engineering. But that of marginal failure is generally more complicate. Engineer should consider many different scenarios to find the root cause. The marginal voltage fail is caused from many different reasons and the analysis from marginal fail is of course very important to screen out healthy devices and also right index of both the yield concerned with process technology and the design methodology. In this paper, the author dealt with three marginal voltage fail case studies: scan chain fail, digital function fail and analog function fail. Through these case studies, LADA successfully defined the fault location and the reason of device alteration was well explained with further study. It is obvious that LADA is very effective way to analyze the marginal fail in case FA engineer doesn’t have much design information because the result is very intuitive and clear. Also it is said that there is no doubt of LADA results because the result of LADA is defined from tester and it is direct indication of changing voltage margin. The root cause of marginal voltage failures were successfully analyzed with LADA, also LVP supported to probe the signal. LADA immediately displayed suspicious location and well explained the results. From In case study 1, LADA detected an exact fault location in the F/F by exciting p-mos performance faster than normal operation at clock inverter. Finally cross section view showed anomaly on contact and poly caused from process instability.In case study 2, LADA detected hold time violation location due to design issue and helped to find out design mistake. In case study 3, it is also effective utilizing LADA not only dynamic function but also static function. But the main difference is there is only junction leakage due to electron hole pair generation.