Failure Analysis Methodology on Resistive Open Defects
Failure Analysis Methodology on Resistive Open Defects
Wednesday, November 12, 2014
Exhibit Hall B3 (George R. Brown Convention Center )
Summary:
We observed that “open” defects resulting in logic failure could result in floating nodes and saturated transistors with photon emission detectable by high sensitivity InGaAs camera. By precisely localizing these emission sites with the help from cad navigation and software layout tracing tools, a failure path could be identified. Further layout analysis or nanoprobing techniques like EBAC analysis can then be employed to narrow down the physical failure analysis inspection region for defect tracing. This paper describes several case studies with the use this failure analysis methodology to successfully localized subtle resistive open defects resulting in yield loss.
We observed that “open” defects resulting in logic failure could result in floating nodes and saturated transistors with photon emission detectable by high sensitivity InGaAs camera. By precisely localizing these emission sites with the help from cad navigation and software layout tracing tools, a failure path could be identified. Further layout analysis or nanoprobing techniques like EBAC analysis can then be employed to narrow down the physical failure analysis inspection region for defect tracing. This paper describes several case studies with the use this failure analysis methodology to successfully localized subtle resistive open defects resulting in yield loss.