Debugging Phase Locked Loop Failures in Integrated Circuit Products
Debugging Phase Locked Loop Failures in Integrated Circuit Products
Thursday, November 13, 2014: 9:15 AM
310 B (George R. Brown Convention Center )
Summary:
A phase locked loop (PLL) is commonly implemented in integrated circuit devices for frequency control. On a final product, PLL sub-building blocks usually do not have external test pins for easy debugging. This complicates fault isolation on PLL failures. This paper presents a systematic wafer level debug approach using tester-based techniques and design simulation to diagnose PLL failures.
A phase locked loop (PLL) is commonly implemented in integrated circuit devices for frequency control. On a final product, PLL sub-building blocks usually do not have external test pins for easy debugging. This complicates fault isolation on PLL failures. This paper presents a systematic wafer level debug approach using tester-based techniques and design simulation to diagnose PLL failures.