21.2
Failure Analysis Methodology on Circular Patch Functional Failure due to Device Parametric Drift
Failure Analysis Methodology on Circular Patch Functional Failure due to Device Parametric Drift
Thursday, November 5, 2015: 1:05 PM
Meeting Room D139 & 140 (Oregon Convention Center )
Summary:
In this paper, we described the debug and analysis process of a challenging case study involving a circular patch functional leakage failure that was induced from device parametric drift due to thicker gate oxide. While yield loss resulting from device parametric drift usually relies on monitoring the Electrical Test MOS structures for failure identification, there was no out-of-control signal from the affected wafers because the impacted region is small with low probability of coverage on tested ET structures. In this type of cases, conventional fault localization approach with static laser beam techniques or photon emission microscopy (PEM) would also be ineffective. Thus, a strong “inquisitive” mindset coupled with the essence of such strong problem solving approach is critical to achieve a breakthrough.
In this paper, we described the debug and analysis process of a challenging case study involving a circular patch functional leakage failure that was induced from device parametric drift due to thicker gate oxide. While yield loss resulting from device parametric drift usually relies on monitoring the Electrical Test MOS structures for failure identification, there was no out-of-control signal from the affected wafers because the impacted region is small with low probability of coverage on tested ET structures. In this type of cases, conventional fault localization approach with static laser beam techniques or photon emission microscopy (PEM) would also be ineffective. Thus, a strong “inquisitive” mindset coupled with the essence of such strong problem solving approach is critical to achieve a breakthrough.