9.3
Failure analysis strategies for multi-stacked memory devices with TSV interconnects

Tuesday, November 3, 2015: 3:45 PM
Meeting Room D139 & 140 (Oregon Convention Center )
Mr. Frank Altmann , Fraunhofer Institute for Mechanics of Materials, Halle, Germany
Mr. Christian Grosse , Fraunhofer Institute for Mechanics of Materials, Halle, Germany
Mr. Falk Naumann , Fraunhofer Institute for Mechanics of Materials, Halle, Germany
Mr. Jens Beyersdorfer , Fraunhofer Institute for Mechanics of Materials, Halle, Germany
Mr. Tony Veches , Micron Technology, Inc., Boise, ID

Summary:

In this paper we will demonstrate new approaches for failure diagnostics of DRAM Memory devices with stacked TSV structures. Especially defect localization by Lock-in-Thermography (LIT) and adapted preparation strategies for TSV sidewall shorts will be discussed. Five times stacked TSV daisy chain samples will be used with different TSV specific electrical failure modes.
See more of: 3D Devices Failure Analysis I
See more of: Technical Program