Mr. Matthew M. Mulholland

Process Engineer
Intel Corporation
Post Silicon Validation
3601 Juliette Lane
M/S SC9-43
Santa Clara, CA
USA 95054

Papers:
19.3 The Changing Role of Advanced Sample Preparation in X-ray Inspection Supporting 2.5D and 3D Sample Failure Analysis 28.1 A Combination Continuous Wave and Pulse Laser Assisted Chemical Etching Processes through Encapsulated IC Packaging