Dr. Martin von Haartman
Dr. Martin von Haartman
Engineering Manager
Intel Corporation
Logic Technology Development
2501 NW 229th Avenue
MS: RA3-353
Hillsboro,
OR
USA
97124
Papers:
1.3
Laser Logic State Imaging Using Transient Voltage Collapse Circuits
5.3
Optical Fault Isolation and Nanoprobing Techniques for the 10nm Technology Node and Beyond
16.1
High Resolution Electron Beam Induced Resistance Change for Fault Isolation with 100nm^2 Localization