Package and Physical Analysis Challenges

Sunday, November 1, 2015: 8:00 AM-11:30 AM
Meeting Room D139 & 140 (Oregon Convention Center )
Session Chairs:  Mr. Chris Richardson, FA Products & Applications, Allied High Tech Products, Inc., Rancho Dominguez, CA and Ms. Susan Li, Failure Analysis Lab, Cypress Semiconductor, San Jose, CA
8:00 AM
Failure Analysis Challenges for Chip Scale Packages
Ms. Susan Li, Cypress Semiconductor
9:00 AM
Flip-Chip and Backside Techniques
Dr. Edward I. Cole Jr., Sandia National Laboratories; Dr. Daniel L. Barton, Sandia National Laboratories; Dr. Karoline Bernhard-Hofer, Infineon
10:00 AM
Break
10:30 AM
SAM vs X-RAY
Dr. Thomas M. Moore, Waviks, Inc.
11:30 AM
Lunch
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