Failure Analysis of Single-bit Charge Loss after Stress and Studies on Silicon Dopant Profile
Failure Analysis of Single-bit Charge Loss after Stress and Studies on Silicon Dopant Profile
Wednesday, November 9, 2016
Summary:
The single-bit charge loss of flash memory after stress has been investigated using TEM with selective chemical etching and TCAD simulation for the effect of silicon dopant profile and electrical failure analysis technique. However, the abnormal dopant profile on the drain-side of the failing bit observed in the TEM does not match the leakage behavior from the simulation. A qualitative model for the degradation process is proposed based on the electrical failure analysis results, it is suggested that the hole generated by avalanche breakdown captured by oxide traps on the drain-side during the stress is the source of leakage current.
The single-bit charge loss of flash memory after stress has been investigated using TEM with selective chemical etching and TCAD simulation for the effect of silicon dopant profile and electrical failure analysis technique. However, the abnormal dopant profile on the drain-side of the failing bit observed in the TEM does not match the leakage behavior from the simulation. A qualitative model for the degradation process is proposed based on the electrical failure analysis results, it is suggested that the hole generated by avalanche breakdown captured by oxide traps on the drain-side during the stress is the source of leakage current.