3D Fault Isolation in 2.5D Device comprising High Bandwidth Memory (HBM) Stacks and Processor Unit Using 3D Magnetic Field Imaging
3D Fault Isolation in 2.5D Device comprising High Bandwidth Memory (HBM) Stacks and Processor Unit Using 3D Magnetic Field Imaging
Wednesday, November 9, 2016: 8:25 AM
108 (Fort Worth Convention Center)
Summary:
Process difficulties and other technology challenges have slowed the implementation of 3D technology into high volume manufacturing well behind the original ITRS expectations. Nevertheless, although full implementation suffered yet another delay, 2.5D through the use of interposer and TSV 3D devices are being already produced, especially in memory devices. These 3D devices (System-in-Package (SiP), wafer-level packaging, Through-Silicon-Vias (TSV), stacked-die, etc.) present major challenges for Failure Analysis (FA) that require novel non-destructive, true 3D Failure Localization techniques. 3D Magnetic field Imaging (MFI), recently introduced, proved to be a natural, useful technique for non-destructively mapping 3D current paths in devices that allowed for submicron vertical resolution. In this paper we apply this novel technique for 3D localization of an electrically failing complex 2.5D device combining 4Hi-High Bandwidth Memory (HBM) devices and a processor unit on a Si interposer.
Process difficulties and other technology challenges have slowed the implementation of 3D technology into high volume manufacturing well behind the original ITRS expectations. Nevertheless, although full implementation suffered yet another delay, 2.5D through the use of interposer and TSV 3D devices are being already produced, especially in memory devices. These 3D devices (System-in-Package (SiP), wafer-level packaging, Through-Silicon-Vias (TSV), stacked-die, etc.) present major challenges for Failure Analysis (FA) that require novel non-destructive, true 3D Failure Localization techniques. 3D Magnetic field Imaging (MFI), recently introduced, proved to be a natural, useful technique for non-destructively mapping 3D current paths in devices that allowed for submicron vertical resolution. In this paper we apply this novel technique for 3D localization of an electrically failing complex 2.5D device combining 4Hi-High Bandwidth Memory (HBM) devices and a processor unit on a Si interposer.