Enhanced Static Fault Localization Methodology on Resistive Open Defects using Photon Emission Microscopy and Layout Defect Prediction

Thursday, November 10, 2016: 8:50 AM
108 (Fort Worth Convention Center)
Dr. Alfred C.T. Quah , GLOBALFOUNDRIES Singapore Pte Ltd, Singapore, Singapore
Mr. D. Nagalingam , GLOBALFOUNDRIES Singapore Pte Ltd, Singapore, Singapore
Mr. G. B. Ang , GLOBALFOUNDRIES Singapore Pte Ltd, Singapore, Singapore
Dr. C.Q. Chen , GLOBALFOUNDRIES Singapore Pte Ltd, Singapore, Singapore
Dr. S.J. Moon , GLOBALFOUNDRIES Singapore Pte Ltd, Singapore, Singapore
Mr. E. Susanto , GLOBALFOUNDRIES Singapore Pte Ltd, Singapore, Singapore
H.H. Ma , GLOBALFOUNDRIES Singapore Pte Ltd, Singapore, Singapore
Ms. S.P. Neo , GLOBALFOUNDRIES Singapore Pte Ltd, Singapore, Singapore
Dr. J.C. Lam , GLOBALFOUNDRIES Singapore Pte Ltd, Singapore, Singapore
Dr. Z.H. Mai , GLOBALFOUNDRIES Singapore Pte Ltd, Singapore, Singapore

Summary:

In this paper, we investigate the effects of a floating input, simulating the impact of an open defect along a logic signal path, on various logic gates test structures fabricated on 40nm process. From this learning, we derived a novel static fault localization method using photon emission microscopy and layout aware analysis to predict and narrow down the potential defect location from the entire failure path into a much smaller segment without EBAC analysis. This method is applied with great success to actual low yield cases from advanced technology nodes, with significant reduction in FA cycle time
See more of: Fault Isolation I
See more of: Technical Program