Analysis of an Asynchronously Generated Race Condition
Analysis of an Asynchronously Generated Race Condition
Monday, November 7, 2016: 1:50 PM
113 (Fort Worth Convention Center)
Summary:
Random timing of an asynchronous Low Voltage Detect (LVD) interrupt during the self-test portion of the reset sequence of a microcontroller caused a corrupted clock state machine. A power on reset, or POR, sequence would recover functionality. This paper describes the methods and techniques used to solve the obstacles in order to discover the root cause of the race condition.
Random timing of an asynchronous Low Voltage Detect (LVD) interrupt during the self-test portion of the reset sequence of a microcontroller caused a corrupted clock state machine. A power on reset, or POR, sequence would recover functionality. This paper describes the methods and techniques used to solve the obstacles in order to discover the root cause of the race condition.