Enabling Electro-Optical Failure-Analysis within Extreme Compression Test Architecture
Enabling Electro-Optical Failure-Analysis within Extreme Compression Test Architecture
Wednesday, November 9, 2016
Summary:
In addition to the ever shrinking technology dimensions and the resulting need for better optical resolution, EFA also needs to keep up with innovations in test-architecture. Driven by the need for much higher test-compression, Nvidia recently changed its DFT architecture to “Extreme-Compression” (XTR) with on-chip pattern generation, MISR based compression of the chain output data and chiplet-based multi-port test pattern release, drastically changing the requirements for test-loop setups necessary to enable the most established EFA techniques such as LVP and SDL (aka DLS, LADA). This paper discusses test-loop requirements in general and gives Advantest 93k specific guidelines on test-pattern release and ATE setup, necessary to enabling all EFA techniques that we’ve been relying on before XTR.
In addition to the ever shrinking technology dimensions and the resulting need for better optical resolution, EFA also needs to keep up with innovations in test-architecture. Driven by the need for much higher test-compression, Nvidia recently changed its DFT architecture to “Extreme-Compression” (XTR) with on-chip pattern generation, MISR based compression of the chain output data and chiplet-based multi-port test pattern release, drastically changing the requirements for test-loop setups necessary to enable the most established EFA techniques such as LVP and SDL (aka DLS, LADA). This paper discusses test-loop requirements in general and gives Advantest 93k specific guidelines on test-pattern release and ATE setup, necessary to enabling all EFA techniques that we’ve been relying on before XTR.