Efficient and Effective Failure Analysis of Low-Resistive Defect in Logic Device Using Layout-aware and Volume Diagnosis
Efficient and Effective Failure Analysis of Low-Resistive Defect in Logic Device Using Layout-aware and Volume Diagnosis
Wednesday, October 31, 2018: 8:00 AM
225AB (Phoenix Convention Center)
Summary:
This study successfully verified that the failure which was not isolated by electrical characterization, was driven by layout-aware and volume diagnosis, and following PFA and TEM perfectly identified low-resistive defect, which could be the critical detractors in process. In addition, those new methodologies efficiently and effectively reduced PFA TAT by 57% with fewer samples than traditional ones because layout-aware diagnosis-driven failure analysis allowed extra electrical isolation effort to be skipped, leading to the fast feedback of yield detractor to fab so that the inline issue would be resolved.
This study successfully verified that the failure which was not isolated by electrical characterization, was driven by layout-aware and volume diagnosis, and following PFA and TEM perfectly identified low-resistive defect, which could be the critical detractors in process. In addition, those new methodologies efficiently and effectively reduced PFA TAT by 57% with fewer samples than traditional ones because layout-aware diagnosis-driven failure analysis allowed extra electrical isolation effort to be skipped, leading to the fast feedback of yield detractor to fab so that the inline issue would be resolved.