Novel carrier measurement methodology for floating gate of sub-20 nm node flash memory using scanning nonlinear dielectric microscopy

Monday, October 29, 2018: 2:40 PM
226BC (Phoenix Convention Center)
Mr. Jun Hirota , Toshiba Memory Corporation, Yokkaichi, Japan
Prof. Yuji Yamagishi , Tohoku University, Sendai, Japan
Dr. Shiro Takeno , Toshiba Memory Corporation, Yokkaichi, Japan
Prof. Yasuo Cho , Tohoku University, Sendai, Japan

See more of: Scanning Probe Analysis I
See more of: Technical Program