A Latent Issue of Via Resistance: Mechanism and Solution

Tuesday, October 30, 2018: 4:30 PM
225AB (Phoenix Convention Center)
Dr. Wentao Qin , ON Semiconductor, Phoenix, AZ
Dr. Scott Donaldson , ON Semiconductor, Pocatello, ID
Dr. Dan Rogers , ON Semiconductor, Pocatello, ID
Dr. Lahcen Boukhanfra , On Semiconductor, Phoenix, AZ
Mr. Julien Thiefain , On Semiconductor, Phoenix, AZ
Ms. Denise Barrientos , ON Semiconductor, Phoenix, AZ
Dr. Gordy Grivna , On Semiconductor, Phoenix, AZ
Dr. Jim steinwall , ON Semiconductor, Phoenix, AZ
Dr. George Chang , ON Semiconductor, Phoenix, AZ
Mr. Jeff Gambino , ON Semiconductor, Gresham, OR

Summary:

An insufficient post WCMP clean left W-oxide on the W plug of a via. The Ti subsequently deposited on the W plug spontaneously reduced the W-oxide to form Ti-oxide over time. The bond energy of TiO2 is higher than those of both WO2 and WO3. The valence electrons therefore are more tightly bound to the ion cores in the Ti-oxide than in the W-oxide, which makes the Ti-oxide more resistive than the W-oxide. Since the W-oxide is less resistive than the Ti-oxide, this processing issue had escaped the in-fab testing, but later developed to have caused a device failure in field. The issue was addressed with a more effective removal of the W oxide after the W CMP. One more example that involved Al reduction of Ta2O5 is provided, which also results in a resistivity increase. A more rigorous in-fab testing to flag such latent issues is needed.