Single Shot Logic Patterns: Increasing Diagnostic Resolution of Logic Failures Utilizing Single Fault Targeting and Constraints

Tuesday, October 30, 2018: 11:00 AM
Exhibit Halls A/B (Phoenix Convention Center)
Mr. Rommel Estores , ON Semiconductor, Oudenaarde, Belgium
Mr. Eric Barbian , ON Semiconductor, Phoenix, AZ

Summary:

This paper will discuss a methodology that helps the analyst understand and complement ATPG diagnosis by using an approach called “single shot logic patterns”. New patterns that each target one singular fault in the area of interest provide the failure analyst with simplified analytical data. This process is repeated for each suspect candidate. The number of times a target fault is detected is increased for better resolution. Aggregating this analytical data with the layout and fan out of the net instances could provide greater resolution into the likely defective area. Furthermore, adding constraints can also be used to further simplify the test and/or control the fan out of failures.