Product Yield, Test & Diagnostics

Tuesday, October 30, 2018: 10:35 AM-11:50 AM
Exhibit Halls A/B (Phoenix Convention Center)
Mr. Amit M. Jakati, GLOBALFOUNDRIES and Mr. Jayant DSouza, Mentor Graphics
10:35 AM
Pattern Matching Rule Ranking Through Design of Experiments and Silicon Validation
Mr. Gaurav Rajavendra Reddy, GLOBALFOUNDRIES Inc.; Dr. Jin Wallner, GLOBALFOUNDRIES Inc.; Ms. Katherina Babich, GLOBALFOUNDRIES Inc.; Dr. Yiorgos Makris, The University of Texas at Dallas
11:00 AM
Single Shot Logic Patterns: Increasing Diagnostic Resolution of Logic Failures Utilizing Single Fault Targeting and Constraints
Mr. Rommel Estores, ON Semiconductor; Mr. Eric Barbian, ON Semiconductor
11:25 AM
Asymmetric Data - Frequency Mapping and Multi Trigger - Probing for Improved Scan Debug
Ms. Anuradha Swaminathan, Intel Corporation; Mr. Eli Abuayob, Intel Corp; Mr. Gitelmkher Konstantine, Intel Corp; Dr. Nathan Bakken, PhD, Intel Corporation
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