Thermal Exposure Effects of Backside Thinned Flip-Chip Device on Visible Light Probing
Thermal Exposure Effects of Backside Thinned Flip-Chip Device on Visible Light Probing
Monday, October 29, 2018: 2:15 PM
225AB (Phoenix Convention Center)
Summary:
Visible Light Probing (VLP) is the evolutionary next-step for Laser Voltage Probing (LVP) and its extensions (LVx). Reducing spot size by decreasing laser wavelength is the only remaining option as Numerical Aperture (NA) and index-of-refraction (n) of Solid Immersion Lenses (SILs) are at their practical limits. Unfortunately, the adoption of VLP is greatly hindered by the stringent requirements on sample preparation, including the “as finished” surface conditions. For 577 nm wavelength VLP systems, thinning of the Silicon (Si) backside to a Remaining Silicon Thickness (RST) of 1-2 µm is required. For 785 nm wavelength, the requirement is 3-5 µm. These values are driven by the strong attenuation of light at the short wavelengths used. SILs place additional requirements on the Device Under Test’s (DUT’s) flatness and smoothness since intimate contact over the SIL’s contact facet (~0.5 mm diameter area, dependent on the particular SIL design) is required to achieve full optical performance over the SIL’s Field-of-View (FOV). Sample preparation systems are now commercially available that successfully prepare the samples to the required RST with some yield. However, they can’t compensate for the effects of underfill shrinkage, which can create surface topography on the Si backside with the pitch of the die solder bumps. This topography can prevent a SIL from making the necessary intimate contact to the die, degrading both resolution and light throughput, which affects Signal-to-Noise Ratio (SNR) of the LVx measurements. In this paper, we report on the findings of our studies into temperature induced silicon surface topography changes during the sample preparation process and potentially during testing, and suggest ways to minimize this effect.
Visible Light Probing (VLP) is the evolutionary next-step for Laser Voltage Probing (LVP) and its extensions (LVx). Reducing spot size by decreasing laser wavelength is the only remaining option as Numerical Aperture (NA) and index-of-refraction (n) of Solid Immersion Lenses (SILs) are at their practical limits. Unfortunately, the adoption of VLP is greatly hindered by the stringent requirements on sample preparation, including the “as finished” surface conditions. For 577 nm wavelength VLP systems, thinning of the Silicon (Si) backside to a Remaining Silicon Thickness (RST) of 1-2 µm is required. For 785 nm wavelength, the requirement is 3-5 µm. These values are driven by the strong attenuation of light at the short wavelengths used. SILs place additional requirements on the Device Under Test’s (DUT’s) flatness and smoothness since intimate contact over the SIL’s contact facet (~0.5 mm diameter area, dependent on the particular SIL design) is required to achieve full optical performance over the SIL’s Field-of-View (FOV). Sample preparation systems are now commercially available that successfully prepare the samples to the required RST with some yield. However, they can’t compensate for the effects of underfill shrinkage, which can create surface topography on the Si backside with the pitch of the die solder bumps. This topography can prevent a SIL from making the necessary intimate contact to the die, degrading both resolution and light throughput, which affects Signal-to-Noise Ratio (SNR) of the LVx measurements. In this paper, we report on the findings of our studies into temperature induced silicon surface topography changes during the sample preparation process and potentially during testing, and suggest ways to minimize this effect.