Package and Physical Analysis Challenges I

Sunday, October 28, 2018: 8:00 AM-10:00 AM
226A (Phoenix Convention Center)
Mr. Chris Richardson, Allied High Tech Products, Inc. and Mr. John Bescup, Jet Propulsion Laboratory
8:00 AM
Chip Scale Packaging and Its Failure Analysis Challenges
Ms. Susan Li, Cypress Semiconductor
9:00 AM
Flip-Chip and Backside Techniques
Dr. Edward I. Cole Jr., Sandia National Laboratories
See more of: Tutorial
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